Peripheral Memory-Mapped Registers
Table 4-10 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F0E0)
Register Acronym
Address Offset
$0
Register Description
Interrupt Priority Register 0
ITCN_IPR0
ITCN_IPR1
ITCN_IPR2
ITCN_IPR3
ITCN_IPR4
ITCN_IPR5
ITCN_IPR6
ITCN_VBA
$1
$2
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Vector Base Address Register
Fast Interrupt Match 0 Register
Fast Interrupt Vector Address Low 0 Register
Fast Interrupt Vector Address High 0 Register
Fast Interrupt Match 1 Register
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
$3
$4
$5
$6
$7
ITCN_FIM0
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
ITCN_IRQP3
$8
$9
$A
$B
$C
$D
$E
$F
$10
$11
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
Reserved
ITCN_ICTRL
$16
Interrupt Control Register
Reserved
Table 4-11 SIM Registers Address Map
(SIM_BASE = $00 F100)
Register Acronym
Address Offset
Register Description
SIM_CTRL
SIM_RSTAT
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_MSHID
SIM_LSHID
SIM_PWR
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Power Control Register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
47
FREESCALE [ Freescale ]
