Peripheral Memory-Mapped Registers
Table 4-8 Analog-to-Digital Converter Registers Address Map (Continued)
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
$E
Register Description
ADC_RSLT2
ADC_RSLT3
ADC_RSLT4
ADC_RSLT5
ADC_RSLT6
ADC_RSLT7
ADC_RSLT8
ADC_RSLT9
ADC_RSLT10
ADC_RSLT11
ADC_RSLT12
ADC_RSLT13
ADC_RSLT14
ADC_RSLT15
ADC_LOLIM0
ADC_LOLIM1
ADC_LOLIM2
ADC_LOLIM3
ADC_LOLIM4
ADC_LOLIM5
ADC_LOLIM6
ADC_LOLIM7
ADC_HILIM0
ADC_HILIM1
ADC_HILIM2
ADC_HILIM3
ADC_HILIM4
ADC_HILIM5
ADC_HILIM6
ADC_HILIM7
ADC_OFFST0
ADC_OFFST1
ADC_OFFST2
ADC_OFFST3
ADC_OFFST4
ADC_OFFST5
Result Register 2
Result Register 3
Result Register 4
Result Register 5
Result Register 6
Result Register 7
Result Register 8
Result Register 9
$F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
$30
$31
Result Register 10
Result Register 11
Result Register 12
Result Register 13
Result Register 14
Result Register 15
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
High Limit Register 0
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
High Limit Register 7
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
45
FREESCALE [ Freescale ]
