Peripheral Memory-Mapped Registers
Table 4-14 Power Supervisor Registers Address Map
(PS_BASE = $00 F140)
Register Acronym
Address Offset
Register Description
PS_CTRL
PS_STAT
$0
$1
Control Register
Status Register
Reserved
Table 4-15 GPIOA Registers Address Map
(GPIOA_BASE = $00 F150)
Address Offset
Register Description
Register Acronym
GPIOA_PUPEN
GPIOA_DATA
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
GPIOA_DDIR
Data Direction Register
GPIOA_PEREN
GPIOA_IASSRT
GPIOA_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOA_IEPOL
GPIOA_IPEND
GPIOA_IEDGE
GPIOA_PPOUTM
GPIOA_RDATA
GPIOA_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
Table 4-16 GPIOB Registers Address Map
(GPIOB_BASE = $00 F160)
Register Acronym
Address Offset
Register Description
GPIOB_PUPEN
GPIOB_DATA
GPIOB_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
GPIOB_PEREN
GPIOB_IASSRT
GPIOB_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOB_IEPOL
GPIOB_IPEND
GPIOB_IEDGE
GPIOB_PPOUTM
GPIOB_RDATA
GPIOB_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
49
FREESCALE [ Freescale ]
