Table 4-17 GPIOC Registers Address Map
(GPIOC_BASE = $00 F170)
Register Acronym
Address Offset
Register Description
GPIOC_PUPEN
GPIOC_DATA
GPIOC_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
GPIOC_PEREN
GPIOC_IASSRT
GPIOC_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOC_IEPOL
GPIOC_IPEND
GPIOC_IEDGE
GPIOC_PPOUTM
GPIOC_RDATA
GPIOC_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
Table 4-18 GPIOD Registers Address Map
(GPIOD_BASE = $00 F180)
Register Acronym
Address Offset
Register Description
GPIOD_PUPEN
GPIOD_DATA
GPIOD_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
GPIOD_PEREN
GPIOD_IASSRT
GPIOD_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOD_IEPOL
GPIOD_IPEND
GPIOD_IEDGE
GPIOD_PPOUTM
GPIOD_RDATA
GPIOD_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
Table 4-19 Programmable Interval Timer 0 Registers Address Map
(PIT0_BASE = $00 F190)
Register Acronym
Address Offset
Register Description
PIT0_CTRL
PIT0_MOD
PIT0_CNTR
$0
$1
$2
Control Register
Modulo Register
Counter Register
56F8036 Data Sheet, Rev. 6
50
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