Peripheral Memory-Mapped Registers
Table 4-7 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F000)
Register Acronym
Address Offset
$0
Register Description
Compare Register 1
TMRA0_COMP1
TMRA0_COMP2
TMRA0_CAPT
TMRA0_LOAD
TMRA0_HOLD
TMRA0_CNTR
TMRA0_CTRL
TMRA0_SCTRL
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_CSCTRL
TMRA0_FILT
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRA0_ENBL
TMRA1_COMP1
TMRA1_COMP2
TMRA1_CAPT
TMRA1_LOAD
TMRA1_HOLD
TMRA1_CNTR
TMRA1_CTRL
TMRA1_SCTRL
TMRA1_CMPLD1
TMRA1_CMPLD2
TMRA1_CSCTRL
TMRA1_FILT
$F
Timer Channel Enable Register
Compare Register 1
Compare Register 2
Capture Register
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRA2_COMP1
TMRA2_COMP2
TMRA2_CAPT
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCTRL
$20
$21
$22
$23
$24
$25
$26
$27
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
43
FREESCALE [ Freescale ]
