Peripheral Memory-Mapped Registers
Table 4-20 Programmable Interval Timer 1 Registers Address Map
(PIT1_BASE = $00 F1A0)
Register Acronym
Address Offset
$0
Register Description
PIT1_CTRL
PIT1_MOD
PIT1_CNTR
Control Register
Modulo Register
Counter Register
$1
$2
Table 4-21 Programmable Interval Timer 2 Registers Address Map
(PIT2_BASE = $00 F1B0)
Register Acronym
Address Offset
Register Description
PIT2_CTRL
PIT2_MOD
PIT2_CNTR
$0
$1
$2
Control Register
Modulo Register
Counter Register
Table 4-22 Digital-to-Analog Converter 0 Registers Address Map
(DAC0_BASE = $00 F1C0)
Register Acronym
Address Offset
Register Description
DAC0_CTRL
DAC0_DATA
DAC0_STEP
DAC0_MINVAL
DAC0_MAXVAL
$0
$1
$2
$3
$4
Control Register
Data Register
Step Register
Minimum Value Register
Maximum Value Register
Table 4-23 Digital-to-Analog Converter 0 Registers Address Map
(DAC1_BASE = $00 F1D0)
Register Acronym
Address Offset
Register Description
DAC1_CTRL
DAC1_DATA
DAC1_STEP
DAC1_MINVAL
DAC1_MAXVAL
$0
$1
$2
$3
$4
Control Register
Data Register
Step Register
Minimum Value Register
Maximum Value Register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
51