Table 4-7 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F000)
Register Acronym
Address Offset
Register Description
Comparator Load Register 1
TMRA2_CMPLD1
TMRA2_CMPLD2
TMRA2_CSCTRL
TMRA2_FILT
$28
$29
$2A
$2B
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRA3_COMP1
TMRA3_COMP2
TMRA3_CAPT
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCTRL
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_CSCTRL
TMRA3_FILT
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
Table 4-8 Analog-to-Digital Converter Registers Address Map
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
Register Description
Control Register 1
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_CLIST 1
ADC_CLIST 2
ADC_CLIST 3
ADC_CLIST 4
ADC_SDIS
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
Control Register 2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Channel List Register 3
Channel List Register 4
Sample Disable Register
Status Register
ADC_STAT
ADC_RDY
Conversion Ready Register
Limit Status Register
Zero Crossing Status Register
Result Register 0
ADC_LIMSTAT
ADC_ZXSTAT
ADC_RSLT0
ADC_RSLT1
Result Register 1
56F8036 Data Sheet, Rev. 6
44
FreescaleSemiconductor
FREESCALE [ Freescale ]
