Table 4-11 SIM Registers Address Map (Continued)
(SIM_BASE = $00 F100)
Register Acronym
Address Offset
Register Description
Reserved
SIM_CLKOUT
SIM_PCR
$A
$B
Clock Out Select Register
Peripheral Clock Rate Register
SIM_PCE0
SIM_PCE1
SIM_SD0
$C
Peripheral Clock Enable Register 0
$D
Peripheral Clock Enable Register 1
$E
Peripheral STOP Disable Register 0
Peripheral STOP Disable Register 1
I/O Short Address Location High Register
I/O Short Address Location Low Register
Protection Register
SIM_SD1
$F
SIM_IOSAHI
SIM_IOSALO
SIM_PROT
SIM_GPSA0
SIM_GPSA1
SIM_GPSB0
SIM_GPSB1
SIM_GPSCD
SIM_IPS0
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
GPIO Peripheral Select Register 0 for GPIOA
GPIO Peripheral Select Register 1 for GPIOA
GPIO Peripheral Select Register 0 for GPIOB
GPIO Peripheral Select Register 1 for GPIOB
GPIO Peripheral Select Register for GPIOC and GPIOD
Internal Peripheral Source Select Register 0 for PWM
Internal Peripheral Source Select Register 1 for DACs
Internal Peripheral Source Select Register 2 for TMRA
Reserved
SIM_IPS1
SIM_IPS2
Table 4-12 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F120)
Register Acronym
Address Offset
Register Description
COP_CTRL
COP_TOUT
COP_CNTR
$0
$1
$2
Control Register
Time-Out Register
Counter Register
Table 4-13 Clock Generation Module Registers Address Map
(OCCS_BASE = $00 F130)
Register Acronym
Address Offset
Register Description
OCCS_CTRL
OCCS_DIVBY
OCCS_STAT
$0
$1
$2
Control Register
Divide-By Register
Status Register
Reserved
OCCS_OCTRL
OCCS_CLKCHK
OCCS_PROT
$5
$6
$7
Oscillator Control Register
Clock Check Register
Protection Register
56F8036 Data Sheet, Rev. 6
48
FreescaleSemiconductor
FREESCALE [ Freescale ]
