Peripheral Memory Mapped Registers
Table 4-18 GPIOC Registers Address Map
(GPIOC_BASE = $00 F120)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
GPIOC_PUPEN
GPIOC_DATA
GPIOC_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Data Register
Data Direction Register
GPIOC_PEREN
GPIOC_IASSRT
GPIOC_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Register
GPIOC_IEPOL
GPIOC_IPEND
GPIOC_IEDGE
GPIOC_PPOUTM
GPIOC_RDATA
GPIOC_DRIVE
Drive Strength Control Register
Table 4-19 GPIOD Registers Address Map
(GPIOD_BASE = $00 F130)
Register Acronym
Address Offset
Register Description
GPIOD_PUPEN
GPIOD_DATA
GPIOD_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
GPIOD_PEREN
GPIOD_IASSRT
GPIOD_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Register
GPIOD_IEPOL
GPIOD_IPEND
GPIOD_IEDGE
GPIOD_PPOUTM
GPIOD_RDATA
GPIOD_DRIVE
Drive Strength Control Register
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
41
FREESCALE [ Freescale ]
