Peripheral Memory Mapped Registers
Table 4-9 Interrupt Control Registers Address Map (Continued)
(ITCN_BASE = $00 F060)
Register Acronym
Address Offset
Register Description
ITCN_FIM1
$9
$A
$B
$C
$D
$E
Fast Interrupt Match 1 Register
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP 0
ITCN_IRQP 1
ITCN_IRQP 2
IRQ Pending Register 1
IRQ Pending Register 2
Reserved
ITCN_ICTRL
$12
Interrupt Control Register
Reserved
Table 4-10 Analog-to-Digital Converter Registers Address Map
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
Register Description
Control Register 1
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_CLIST 1
ADC_CLIST 2
ADC_SDIS
$0
$1
Control Register 2
$2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
$3
$4
$5
ADC_STAT
$6
ADC_LIMSTAT
ADC_ZXSTAT
ADC_RSLT0
ADC_RSLT1
ADC_RSLT2
ADC_RSLT3
ADC_RSLT4
ADC_RSLT5
ADC_RSLT6
ADC_RSLT7
ADC_LOLIM0
ADC_LOLIM1
ADC_LOLIM2
ADC_LOLIM3
ADC_LOLIM4
ADC_LOLIM5
$7
Limit Status Register
Zero Crossing Status Register
Result Register 0
$8
$9
$A
$B
$C
$D
$E
$F
Result Register 1
Result Register 2
Result Register 3
Result Register 4
Result Register 5
Result Register 6
$10
$11
$12
$13
$14
$15
$16
Result Register 7
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
37
FREESCALE [ Freescale ]
