Introduction
Table 4-22 Flash Module Registers Address Map (Continued)
(FM_BASE = $00 F400)
Register Acronym
Address Offset
Register Description
User Status Register
FM_USTAT
FM_CMD
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
Command Register
Reserved
Reserved
Reserved
FM_DATA
Data Buffer Register
Reserved
Reserved
FM_OPT1
Optional Data 1 Register
Reserved
FM_TSTSIG
$1D
Test Array Signature Register
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in
order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Ability to drive initial address on the address bus after reset
For further information, see Table 4-2, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 46 interrupt
sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value
of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority
and number 45 is the lowest.
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
43
FREESCALE [ Freescale ]
