Peripheral Memory Mapped Registers
Table 4-12 Serial Peripheral Interface Registers Address Map
(SPI_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
SPI_SCTRL
SPI_DSCTRL
SPI_DRCV
SPI_DXMIT
$0
$1
$2
$3
Status and Control Register
Data Size and Control Register
Data Receive Register
Data Transmit Register
2
Table 4-13 I C Registers Address Map
(I2C_BASE = $00 F0D0)
Register Acronym
Address Offset
Register Description
I2C_ADDR
I2C_FDIV
I2C_CTRL
I2C_STAT
I2C_DATA
I2C_NFILT
$0
$1
$2
$3
$4
$5
Address Register
Frequency Divider Register
Control Register
Status Register
Data Register
Noise Filter Register
Table 4-14 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F0E0)
Register Acronym
Address Offset
Register Description
COP_CTRL
COP_TOUT
COP_CNTR
$0
$1
$2
Control Register
Time-Out Register
Counter Register
Table 4-15 Clock Generation Module Registers Address Map
(OCCS_BASE = $00 F0F0)
Register Acronym
Address Offset
Register Description
OCCS_CTRL
OCCS_DIVBY
OCCS_STAT
$0
$1
$2
Control Register
Divide-By Register
Status Register
Reserved
OCCS_SHUTDN
OCCS_OCTRL
$4
$5
Shutdown Register
Oscillator Control Register
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
39
FREESCALE [ Freescale ]
