Peripheral Memory Mapped Registers
Table 4-7 Quad Timer Registers Address Map (Continued)
(TMR_BASE = $00 F000)
Register Acronym
Address Offset
$12
Register Description
TMR1_CAPT
TMR1_LOAD
TMR1_HOLD
TMR1_CNTR
TMR1_CTRL
Capture Register
Load Register
$13
$14
$15
$16
$17
$18
$19
$1A
Hold Register
Counter Register
Control Register
TMR1_SCTRL
TMR1_CMPLD1
TMR1_CMPLD2
TMR1_CSCTRL
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMR2_COMP1
TMR2_COMP2
TMR2_CAPT
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMR2_LOAD
TMR2_HOLD
TMR2_CNTR
TMR2_CTRL
Load Register
Hold Register
Counter Register
Control Register
TMR2_SCTRL
TMR2_CMPLD1
TMR2_CMPLD2
TMR2_CSCTRL
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMR3_COMP1
TMR3_COMP2
TMR3_CAPT
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMR3_LOAD
TMR3_HOLD
TMR3_CNTR
TMR3_CTRL
Load Register
Hold Register
Counter Register
Control Register
TMR3_SCTRL
TMR3_CMPLD1
TMR3_CMPLD2
TMR3_CSCTRL
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
35