The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-6 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
Timer
PWM
ITCN
ADC
SCI
TMRn
PWM
ITCN
ADC
SCI
X:$00 F000
X:$00 F040
X:$00 F060
X:$00 F080
X:$00 F0B0
X:$00 F0C0
X:$00 F0D0
4-7
4-8
4-9
4-10
4-11
4-12
4-13
SPI
SPI
I2C
I2C
COP
COP
X:$00 F0E0
X:$00 F0F0
X:$00 F100
X:$00 F110
X:$00 F120
X:$00 F130
X:$00 F140
X:$00 F160
X:$00 F400
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
CLK, PLL, OSC, TEST
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SIM
OCCS
GPIOA
GPIOB
GPIOC
GPIOD
SIM
Power Supervisor
FM
PS
FM
Table 4-7 Quad Timer Registers Address Map
(TMR_BASE = $00 F000)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMR0_COMP1
TMR0_COMP2
TMR0_CAPT
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMR0_LOAD
TMR0_HOLD
TMR0_CNTR
TMR0_CTRL
Load Register
Hold Register
Counter Register
Control Register
TMR0_SCTRL
TMR0_CMPLD1
TMR0_CMPLD2
TMR0_CSCTRL
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMR1_COMP1
TMR1_COMP2
$10
$11
Compare Register 1
Compare Register 2
56F8014 Technical Data, Rev. 9
34
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
