Peripheral Memory Mapped Registers
Table 4-5 EOnCE Memory Map
Address
X:$FF FFFF
Register Acronym
Register Name
OTX1 / ORX1
Transmit Register Upper Word
Receive Register Upper Word
X:$FF FFFE
OTX / ORX (32 bits)
Transmit Register
Receive Register
X:$FF FFFD
X:$FF FFFC
X:$FF FFFB - X:$FF FFA1
X:$FF FFA0
X:$FF FF9F
X:$FF FF9E
X:$FF FF9D
X:$FF FF9C
X:$FF FF9B
X:$FF FF9A
X:$FF FF99
OTXRXSR
OCLSR
Transmit and Receive Status and Control Register
Core Lock / Unlock Status Register
Reserved
OCR
Control Register
Instruction Step Counter
OSCNTR (24 bits)
OSR
Instruction Step Counter
Status Register
OBASE
Peripheral Base Address Register
Trace Buffer Control Register
Trace Buffer Pointer Register
Trace Buffer Register Stages
OTBCR
OTBPR
X:$FF FF98
OTB (21 - 24 bits/stage) Trace Buffer Register Stages
Breakpoint Unit Control Register
X:$FF FF97
X:$FF FF96
OBCR (24 bits)
OBAR1 (24 bits)
OBAR2 (32 bits)
OBMSK (32 bits)
OBCNTR
Breakpoint Unit Control Register
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 2
Breakpoint Unit Address Register 2
Breakpoint Unit Mask Register 2
Breakpoint Unit Mask Register 2
Reserved
X:$FF FF95
X:$FF FF94
X:$FF FF93
X:$FF FF92
X:$FF FF91
X:$FF FF90
X:$FF FF8F
X:$FF FF8E
X:$FF FF8D
X:$FF FF8C
X:$FF FF8B
X:$FF FF8A
X:$FF FF89 - X:$FF FF00
EOnCE Breakpoint Unit Counter
Reserved
Reserved
Reserved
OESCR
External Signal Control Register
Reserved
4.6 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-6 summarizes base addresses for the set of peripherals on the 56F8014 device. Peripherals are
listed in order of the base address.
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
33
FREESCALE [ Freescale ]
