F81867
IRQ_MODE1 and IRQ_MODE0 will select the UART5 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
01 : Sharing IRQ active high edge mode.
10 : Sharing IRQ active high Level mode.
3
IRQ_MODE1
R/W LRESET#
0
-
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
Reserved.
2
Reserved
-
-
Select the FIFO depth.
00: 16-byte FIFO.
1-0
FIFO_MODE
R/W LRESET#
00h 01: 32-byte FIFO.
10: 64-byte FIFO.
11: 128-byte FIFO.
7.20 μC Side Registers
The μC side registers are basically accessed by μC with the MOVX instruction. Every device (peripheral) has its
own base address. The address mapping is list as following table.
Device
INTC
Base Address
0x1000
0x1100
0x1200
0x1300
0x1400
0x1500
0x1F00
0x2000
0x2100
0x2200
0x2300
0x2400
0x2500
0x2600
0x3000
0x3100
0x3200
Range
Remark
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
Interrupt Control
General Control
GCTRL
PWM
SRAM1
SRAM2
E2H
EC to host
Embedded Flash
HWM
Could accessed by host side
Could accessed by host side
GPIO
KBC
ACPI
CFG
Configuration; Could be accessed by host side
Could be accessed by host side
RAM
CIR
μC_SFR
μC_RAM
DBPORT
For Debug Port only
For Debug Port only
For Debug Port only
207
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
