F81867
9bit-mode Slave Address Register ⎯ Index F4h
Bit
Name
R/W
Default
Description
Reset
This byte accompanying with SADEN will determine the given address and
broadcast address in 9-bit mode. The UART will response to both given and
broadcast address.
Following description determines the given address and broadcast address:
21. given address: If bit n of SADEN is “0”, then the corresponding bit of
SADDR is don’t care.
22. broadcast address: If bit n of ORed SADDR and SADEN is “0”, don’t care
that bit. The remaining bit which is “1” is compared to the received
address.
7-0
SADDR
R/W LRESET#
00h
Ex.
SADDR
SADEN
0101_1100b
1111_1001b
0101_1xx0b
1111_11x1b
Given Address
Broadcast Address
9bit-mode Slave Address Mask Register ⎯ Index F5h
Bit
Name
R/W Reset Default
Description
This byte accompanying with SADDR will determine the given address and
broadcast address in 9-bit mode. The UART will response to both given and
broadcast address.
Following description determines the given address and broadcast address:
23. given address: If bit n of SADEN is “0”, then the corresponding bit of
SADDR is don’t care.
24. broadcast address: If bit n of ORed SADDR and SADEN is “0”, don’t care
that bit. The remaining bit which is “1” is compared to the received
address.
7:0
SADEN
R/W LRESET#
00h
Ex.
SADDR
SADEN
0101_1100b
1111_1001b
0101_1xx0b
1111_11x1b
Given Address
Broadcast Address
FIFO Select Register ⎯ Index F6h
Bit
Name
R/W Reset Default
Description
0: TX will start transmit immediately after writing THR.
1: TX will delay 1 bit time to transmit after writing THR.
0: TX will assert interrupt when THR is empty.
1: TX will assert interrupt when THR and shift register is empty.
The RX FIFO threshold select.
7
TX_DEL_1BIT
R/W LRESET#
R/W LRESET#
0
0
6
TX_INT_MODE
00: FIFO threshold is set by RXFTHR.
5-4
RXFTHR_MODE
R/W LRESET#
0
01: FIFO threshold will be 2X of RXFTHR.
10: FIFO threshold will be 4X of RXFTHR.
11: FIFO threshold will be 8X of RXFTHR.
206
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
