F71872
7
6
5
4
3
2
Reserved
R
0
0
0
0
0
0
Reserved. Read will return 0.
Watchdog is timeout. When the watchdog is timeout, this bit will be set to one.
If set to 1, write 1 will clear this bit. Write 0, no effect.
STS_WD_TMOUT
WD_ENABLE
WD_PULSE
WD_UNIT
R/W
R/W
R/W
R/W
R/W
Enable watchdog timer.
Watchdog output level or pulse. If set 0 (default), the pin of watchdog is level
output. If write 1, the pin will output with a pulse.
Watchdog unit select. Default 0 is select second. Write 1 to select minute.
Program WD output level. If set to 1 and watchdog asserted, the pin will be
high. If set to 0 and watchdog asserted, this pin will drive low (default).
WD_HACTIVE
Watchdog pulse width selection. If the pin output is selected to pulse mode.
The pulse width can be choice.
00b – 1m second.
1-0 WD_PSWIDTH
R/W
00
01b – 25m second.
10b – 125m second
11b – 5 second
7.9.3.7 Watchdog Timer Range Register Index 05h
Bit
Name
R/W Default
Description
Watchdog timing range from 0 ~ 255. The unit is either second or minute
programmed by the watchdog timer control register bit3.
7-0
WD_TIME
R/W
00h
7.10ACPI and PME Registers
7.10.1 Logic Device Number Register
Logic Device Number Register Index 07H
Bit
Name
R/W Default
Description
103
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
