CMS4A16LAx–75Ex
T0
T2
T3
T1
T4
T5
CLK
Command
Read
Read
Read
Read
NOP
NOP
Bank
Col n
Bank
Col a
Bank
Col x
Bank
Col m
Address
DQ
Dout
Dout
Dout
x
Dout
m
n
a
CAS Latency=2
T0
T2
T3
T1
T4
T5
T6
CLK
Command
Address
Read
Read
Read
Read
NOP
NOP
NOP
Bank
Col n
Bank
Col a
Bank
Col x
Bank
Col m
Dout
n
Dout
a
Dout
x
Dout
m
DQ
CAS Latency=3
Figure 5. Random Read Accesses for CAS Latency =1,2,3
A Read Burst can be terminated by a subsequent Write com-
mand, and data from a fixed length READ burst may be
immediately followed by data from a WRITE command (subject
to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last
desired) data element from the READ burst, provided that I/O
contention can be avoided. In a given system design, there may
be a possibility that the device driving the input data will go
Low-Z before the SDRAM DQs go High-Z. In this case, at least
a single-cycle delay should occur between the last read data
and the WRITE command. The DQM input is used to avoid I/O
contention, as shown in Figure 6. and Figure 7. . The DQM
signal must be asserted (HIGH) at least two clocks prior to the
WRITE command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE comma-
nd is registered, the DQs will go High-Z (or remain High-Z),
regardless of the state of the DQM signal, provided the DQM
22
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
