CMS4A16LAx–75Ex
was active on the clock just prior to the WRITE command that
truncated the READ command. The DQM signal must be as-
serted prior to the WRITE command (DQM latency is zero
clocks for input buffers) to ensure that the written data is not
masked. Figure 6. shows the case where the clock frequency
allows for bus contention to be avoided without adding a NOP
cycle, and Figure 7. shows the case with the additional NOP
cycle.
T0
T2
T3
T1
T4
CLK
DQM
tCK
Command
Address
Read
NOP
NOP
NOP
Write
Bank
Col n
Bank
Col b
tHZ
Dout
n
Din
b
DQ
CAS Latency=3
tDS
Figure 6. Read to Write
23
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
