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CMS4A16LAF 参数 Datasheet PDF下载

CMS4A16LAF图片预览
型号: CMS4A16LAF
PDF下载: 下载PDF文件 查看货源
内容描述: 128M ( 8Mx16 )低功耗SDRAM [128M(8Mx16) Low Power SDRAM]
分类和应用: 动态存储器
文件页数/大小: 46 页 / 616 K
品牌: FIDELIX [ FIDELIX ]
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CMS4A16LAx–75Ex  
A fixed-length READ burst or a full-page burst may be fol-  
lowed by, or truncated with, a PRECHARGE command to the  
same bank. The PRECHARGE command should be issued  
x cycles before the clock edge at which the last desired data  
element is valid, where x equals the CAS latency minus one.  
This is shown in Figure 9. for each possible CAS latency; data  
element n + 3 is either the last of a burst of four or the last  
desired of a longer burst. Following the PRECHARGE comman-  
d, a subsequent command to the same bank cannot be issued  
until tRP is met. Note that part of the row precharge time is  
hidden during the access of the last data element(s). The  
BURST TERMINATE command should be issued x cycles  
before the clock edge at which the last desired data element is  
valid, where x equals the CAS latency minus one. This is  
shown in Figure 10. for each possible CAS latency; data  
element n + 3 is the last desired data element of a longer burst.  
T0  
T2  
T3  
T1  
T4  
T5  
T6  
T7  
CLK  
tRP  
Read  
NOP  
NOP  
NOP  
Precharge  
NOP  
NOP  
Active  
Command  
X=0cycles  
Bank a  
Col n  
Bank  
(a or all)  
Bank a  
Row  
Address  
DQ  
Dout  
n
Dout  
n+1  
Dout  
n+2  
Dout  
n+3  
CAS Latency=1  
T0  
T2  
T3  
T1  
T4  
T5  
T6  
T7  
CLK  
tRP  
Command  
Read  
NOP  
NOP  
NOP  
Precharge  
NOP  
NOP  
Active  
X=1cycles  
Bank a  
Col n  
Bank  
(a or all)  
Bank a  
Row  
Address  
DQ  
Dout  
n
Dout  
n+1  
Dout  
n+2  
Dout  
n+3  
CAS Latency=2  
Figure 9. Read to Precharge  
25  
Rev. 0.5, May. ‘07  
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