CMS4A16LAx–75Ex
T0
T2
T3
T1
T4
T5
T6
T7
CLK
tRP
Command
Read
NOP
NOP
NOP
Precharge
NOP
NOP
Active
X=2cycles
Bank a
Col n
Bank
(a or all)
Bank a
Row
Address
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency=3
Figure 9. Read to Precharge
T0
T2
T3
T1
T4
T5
T6
T7
CLK
Burst
Terminate
Command
Read
NOP
NOP
NOP
NOP
NOP
NOP
X=0cycles
Bank a
Col n
Address
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency=1
Figure 10. Terminating a Read Burst
26
Rev. 0.5, May. ‘07