CMS4A16LAx–75Ex
AC Characteristics
AC Characteristics
Parameter
-75
Symbol
Units
Min
1
Max
Last data-in to new READ/WRITE command[40.]
Last data-in to PRECHARGE command[43.]
LOAD MODE REGISTER command to ACTIVE or REFRESH command[44.]
CL=3
tCDL
tRDL
tCK
tCK
tCK
tCK
tCK
tCK
2
tMRD
2
tROH(3)
tROH(2)
tROH(1)
3
Data-out to high-impedance from PRECHARGE command[40.]
CL=2
CL=1
2
1
Note :
33. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states
(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate.
34.
tAC for -133Mhz at CL=3 with no load is 4.5ns and is guaranteed by design.
35. tAC for -133Mhz at CL=3 and VDD of 1.8V is 6.5ns.
36. AC characteristics assume tT = 1ns.
37. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -133Mhz after the first clock delay, after the last WRITE is executed. May not exceed limit
set for precharge mode.
38. CLK must be toggled a minimum of two times during this period.
39. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
40. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.
41. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.
42. Timing actually specified by tWR. ( tDPL is 1CLK at 100Mhz or tDPL is 2CLK at 133Mhz )
43. JEDEC and PC100 specify three clocks.
18
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
