CMS4A16LAx–75Ex
T0
T2
T3
T1
T4
T5
CLK
DQM
tCK
Command
Address
Read
NOP
NOP
NOP
NOP
Write
Bank
Col n
Bank
Col b
tHZ
Dout
n
Din
b
DQ
CAS Latency=3
tDS
Figure 7. Read to Write with extra clock cycle
T0
T2
T3
T1
T4
T5
T6
T7
T8
CLK
CMD
Read
Write
Read masked by write
DQM
DQ
Din
n+1
Din
n+3
Din
n
Din
n+2
CMD
DQM
DQ
Read
Write
Read masked by DQM
Din
Din
n+3
Din
n
Din
n+2
n+1
CMD
DQM
Read
Write
Read CAS=2
Din
n+1
Din
n+3
Dout
n
Din
n
Din
n+2
DQ
Figure 8. Read Interrupted by Write with DQM ; CAS Latency =2
24
Rev. 0.5, May. ‘07