CMS4A16LAx–75Ex
Table 8. IDD Specifications and Conditions [21.22.26.27.]
Parameter
.
Description
-75
Units
Operating Current: Active Mode; Burst =2 ; Read or Write ; tRC ≥ tRC(min);
CAS Latency =3 [28.29.30.] , tCK=10ns
IDD
1
50
0.3
10
2
㎃
㎃
㎃
㎃
㎃
IDD2P
IDD2N
IDD3P
IDD3N
Precharge Standby Current in power down mode : CKE ≤ VIL(max) , tCK=10ns
Precharge Standby Current in non power down mode : CKE ≥ VIH(min),
/CS ≥ VIH(min) [28.29.30,31.] , tCK=10ns
Active Standby Current in power down mode; CKE ≤ VIL(max) [28.29,30.31.], tCK=10ns
Active Standby Current in non power down mode (One Bank Active);
CKE ≥ VIH(min), /CS ≥ VIH(min) [28.29,30.31.], tCK=10ns
20
Operating Current: Burst Mode: Continuous Burst ; Read or Write : All banks
Active, CAS Latency =3[28.29.30.] , tCK=10ns
IDD
IDD
4
5
50
㎃
Auto Refresh Current : tRC ≥ tRC(min), tCK=10ns
Self Refresh Current : CKE ≤ 0.2V, 4 Banks, tCK= ∞
Self Refresh Current : CKE ≤ 0.2V, 2 Banks , tCK= ∞
Self Refresh Current : CKE ≤ 0.2V, 1 Banks, tCK= ∞
120
400
300
250
㎃
㎂
㎂
㎂
IDD
6
I
DD7
Deep power down, tCK= ∞
10
㎂
Note :
21. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40°C = TA = +85°C for IT parts) is ensured.
22. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be
powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh
requirement is exceeded.
23. All states and sequences not shown are illegal or reserved.
24. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
25. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.
26. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is referenced
at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.
27. IDD specifications are tested after the device is properly initialized.
28. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
29. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.
30. Input signals are changed one time during 20ns.
31. Unless otherwise note, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
32. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD 6 limit is actually a nominal value and does not result in a fail value
Capacitance[]
Parameter
CIN
Description
Test Conditions
Max
4
Units
pF
Input Capacitance
Output Capacitance
TA=25℃, f=1Mhz, VDD(typ)
COUT
6
pF
VDDQ/2
AC Test Loads
50Ω
Z0=50Ω
OUTPUT
30pF
16
Rev. 0.5, May. ‘07
FIDELIX [ FIDELIX ]
