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CMS4A16LAF 参数 Datasheet PDF下载

CMS4A16LAF图片预览
型号: CMS4A16LAF
PDF下载: 下载PDF文件 查看货源
内容描述: 128M ( 8Mx16 )低功耗SDRAM [128M(8Mx16) Low Power SDRAM]
分类和应用: 动态存储器
文件页数/大小: 46 页 / 616 K
品牌: FIDELIX [ FIDELIX ]
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CMS4A16LAx–75Ex  
AUTO REFRESH  
DEEP POWER DOWN  
AUTO REFRESH is used during normal operation of the  
SDRAM. This command is nonpersistent, so it must be issued  
each time a refresh is required. All active banks must be  
PRECHARGED prior to issuing an AUTO REFRESH command.  
The AUTO REFRESH command should not be issued until the  
minimum tRP has been met after the PRECHARGE command.  
The addressing is generated by the internal refresh controller.  
The address bits thus are a “Don’t Care” during an AUTO  
REFRESH command. The Fidelix 128Mb SDRAM requires  
4,096 AUTO REFRESH cycles every 64ms (tREF), regardless  
of width option. Providing a distributed AUTO REFRESH  
command every 15.625µs will meet the refresh requirement and  
ensure that each row is refreshed.  
Deep Power Down Mode is an operating mode to achieve extreme  
power reduction by cutting the power of the whole memory array of  
the device. Data will not be retained once the device enters DPD  
Mode. Full initialization is required when the device exits from DPD  
Mode. [Figure 29.30]  
Alternatively, 4,096 AUTO REFRESH commands can be issued  
in a burst at the minimum cycle rate (tRFC*2), once every 64ms.  
SELF REFRESH  
The SELF REFRESH command can be used to retain data in  
the SDRAM( without external clocking), even if the rest of the  
system is powered down. The SELF REFRESH command is  
initiated like an AUTO REFRESH command except CKE is  
disabled (LOW). Once the SELF REFRESH command is reg-  
istered, all the inputs to the SDRAM become “Don’t Care” with  
the exception of CKE, which must remain LOW. Once self  
refresh mode is engaged, the SDRAM provides its own internal  
clocking, causing it to perform its own AUTO REFRESH cycles.  
The SDRAM must remain in self refresh mode for a minimum  
period equal to tRAS and may remain in self refresh mode for  
an indefinite period beyond that.The procedure for exiting self  
refresh requires a sequence of commands. First, CLK must be  
stable (meet the clock specifications in the AC characteristics)  
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM  
must have NOP commands issued (a minimum of two clocks)  
for tXSR because time is required for the completion of any  
internal refresh in progress. Upon exiting the self refresh mode,  
AUTO REFRESH commands must be issued every 15.625µs or  
less as both SELF REFRESH and AUTO REFRESH utilize he  
row refresh counter.  
14  
Rev. 0.5, May. ‘07