XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
When these interrupt enable bits are set and one or more Loss of Signals are present in the incoming DS1
frame, the XRT86L30 framer will declare Receive Loss of Signal by doing the following:
•
Set the Receive Loss of Signal bit of the Alarm and Error Status Register to one indicating there is one or
more Loss of Signals. This status indicator is valid until the Framer Interrupt Status Register is read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive Loss of Signal status bits of the Alarm and Error Status Register.
ALARM AND ERROR STATUS REGISTER (AESR) (ADDRESS = 0X0B02H)
B
IT
B
IT
N
AME
B
IT
TYPE
BIT DESCRIPTION
N
UMBER
4
Receive Loss of
Signal State
RUR /
WC
0 - There is no change of Loss of Signal state in the incoming DS1 payload
data.
1 - There is change of Loss of Signal state in the incoming DS1 payload
data.
230
EXAR [ EXAR CORPORATION ]
