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XRT86L30IV 参数 Datasheet PDF下载

XRT86L30IV图片预览
型号: XRT86L30IV
PDF下载: 下载PDF文件 查看货源
内容描述: 单一T1 / E1 / J1成帧器/ LIU COMBO [SINGLE T1/E1/J1 FRAMER/LIU COMBO]
分类和应用:
文件页数/大小: 284 页 / 1793 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT86L30  
SINGLE T1/E1/J1 FRAMER/LIU COMBO  
REV. 1.0.1  
2. Each interval with a valid YEL flag increments a flag counter which declares YEL alarm when 80 valid  
intervals have been accumulated.  
3. An interval without valid YEL flag decrements the flag counter. The YEL alarm is removed when the  
counter reaches zero.  
If Yellow Alarm condition is present in the incoming DS1 frame, the XRT86L30 framer can generate a Receive  
Yellow Alarm State Change interrupt associated with the setting of Receive Yellow Alarm State Change bit of  
the Alarm and Error Status Register to one.  
To enable the Receive Yellow Alarm State Change interrupt, the Receive Yellow Alarm State Change Interrupt  
Enable bit of the Alarm and Error Interrupt Enable Register (AEIER) has to be set to one. In addition, the Alarm  
and Error Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.  
The table below shows configurations of the Receive Yellow Alarm State Change Interrupt Enable bit of the  
Alarm and Error Interrupt Enable Register (AEIER).  
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (ADDRESS = 0X0B03H)  
B
IT  
B
IT  
N
AME  
B
IT  
TYPE  
BIT DESCRIPTION  
N
UMBER  
0
Receive Yellow  
Alarm State  
R/W  
0 - The Receive Yellow Alarm State Change interrupt is disabled. Any state  
change of Receive Yellow Alarm will not generate an interrupt.  
Change Interrupt  
Enable  
1 - The Receive Yellow Alarm State Change interrupt is enabled. Any state  
change of Receive Yellow Alarm will generate an interrupt.  
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable  
Register.  
BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0X0B01H)  
B
IT  
B
IT  
N
AME  
B
IT  
TYPE  
BIT DESCRIPTION  
N
UMBER  
1
Alarm and Error  
Interrupt Enable  
R/W  
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-  
ister (AEISR) is disabled.  
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-  
ister (AEISR) is enabled.  
When these interrupt enable bits are set and Yellow Alarm is present in the incoming DS1 frame, the  
XRT86L30 framer will declare Yellow Alarm by doing the following:  
Set the read-only Receive Yellow Alarm State bit of the Alarm and Error Status Register (AESR) to one  
indicating there is Yellow Alarm detected in the incoming DS1 frame.  
Set the Receive Yellow Alarm State Change bit of the Alarm and Error Status Register to one indicating there  
is a change in state of Yellow Alarm. This status indicator is valid until the Framer Interrupt Status Register is  
read.  
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control  
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status  
indicators.  
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