XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0X0B01H)
B
IT
B
IT
N
AME
B
IT
TYPE
BIT DESCRIPTION
N
UMBER
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
When these interrupt enable bits are set and one or more Bipolar Violations are present in the incoming DS1
frame, the XRT86L30 framer will declare Receive Bipolar Violation by doing the following:
•
Set the Receive Bipolar Violation bit of the Alarm and Error Status Register to one indicating there are one or
more Bipolar Violations. This status indicator is valid until the Framer Interrupt Status Register is read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive Bipolar Violation status bits of the Alarm and Error Status Register.
ALARM AND ERROR STATUS REGISTER (AESR) (ADDRESS = 0X0B02H)
B
IT
B
IT
N
AME
B
IT
TYPE
BIT DESCRIPTION
N
UMBER
3
Receive Bipolar
Violation State
Change
RUR /
WC
0 - There is no change of Bipolar Violation state in the incoming DS1 pay-
load data.
1 - There is change of Bipolar Violation state in the incoming DS1 payload
data.
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (ADDRESS = 0X0B03H)
B
IT
B
IT
N
AME
B
IT
TYPE
BIT DESCRIPTION
N
UMBER
4
Receive Loss of
Signal Interrupt
Enable
R/W
0 - The Receive Loss of Signal interrupt is disabled. Occurrence of Loss of
Signals will not generate an interrupt.
1 - The Receive Loss of Signal interrupt is enabled. Occurrence of Loss of
Signals will generate an interrupt.
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0X0B01H)
B
IT
B
IT
N
AME
B
IT
TYPE
BIT DESCRIPTION
N
UMBER
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
229
EXAR [ EXAR CORPORATION ]
