ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
áç
REV. 5.0.0
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C650A in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A.
B.
C.
D.
E.
F.
LSR bit-0 indicates there is data in RHR or RX FIFO.
LSR bit-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
LSR bits 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
LSR bit-5 indicates THR is empty.
LSR bit-6 indicates when both the transmit FIFO and TSR are empty.
LSR bit-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Holding Register empty interrupt (default).
• Logic 1 = Enable Transmit Holding Register empty interrupt.
IER[2]: Receive Line Status Interrupt Enable
Any change of state of the LSR register bits 1, 2, 3 or 4 will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt either when the character with errors is next
to be read out of the FIFO (XFR[3] = 0) or when the received chracter is received (XFR[3] = 1).
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See “Sleep Mode & Wake-up Indicator” on page 21.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See “Auto Xon/Xoff (Software) Flow
Control” on page 18.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from LOW to HIGH.
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EXAR [ EXAR CORPORATION ]
