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ST16C650 参数 Datasheet PDF下载

ST16C650图片预览
型号: ST16C650
PDF下载: 下载PDF文件 查看货源
内容描述: 具有32字节FIFO 2.90V至5.5V UART [2.90V TO 5.5V UART WITH 32-BYTE FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 53 页 / 631 K
品牌: EXAR [ EXAR CORPORATION ]
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ST16C650A  
2.90V TO 5.5V UART WITH 32-BYTE FIFO  
REV. 5.0.0  
FCR[2]: TX FIFO Reset  
This bit is only active when FCR bit-0 is a ‘1’.  
Logic 0 = No transmit FIFO reset (default).  
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not  
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.  
FCR[3]: DMA Mode Select  
Controls the behavior of the TXRDY# and RXRDY# pins. See “DMA Mode” on page 11.  
Logic 0 = DMA Mode disabled (default).  
Logic 1 = DMA Mode enabled.  
FCR[5:4]: Transmit FIFO Trigger Select  
(logic 0 = default, TX trigger level = one)  
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when  
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that  
the FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. EFR bit-4  
must be set to ‘1’ before these bits can be accessed.  
FCR[7:6]: Receive FIFO Trigger Select  
(logic 0 = default, RX trigger level =1).  
The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the  
receiver FIFO interrupt. Table 10 shows the complete selections..  
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION WITH AUTO RTS HYSTERESIS  
TRANSMIT INT RECEIVE INT  
AUTO RTS  
DE-ASSERT  
AUTO RTS  
RE-ASSERT  
FCR  
BIT-7  
FCR  
BIT-6  
FCR  
BIT-5  
FCR  
BIT-4  
TRIGGER  
LEVEL  
TRIGGER  
LEVEL  
COMPATIBILITY  
0
0
1
1
0
1
0
1
16  
8
16C650A compati-  
ble.  
24  
30  
0
0
1
1
0
1
0
1
8
16  
24  
28  
28  
0
8
16  
24  
28  
16  
24  
4.6  
Line Control Register (LCR) - Read/Write  
The Line Control Register is used to specify the asynchronous data communication format. The word or  
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this  
register.  
LCR[1:0]: TX and RX Word Length Select  
These two bits specify the word length to be transmitted or received.  
BIT-1  
BIT-0  
WORD LENGTH  
0
0
1
1
0
1
0
1
5 (default)  
6
7
8
29  
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