ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
áç
REV. 5.0.0
TABLE 8: UART CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1.
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0/
Bit-6
Bit-6
0/
Bit-5
Bit-5
0/
Bit-4
Bit-4
0/
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
IER RD/WR
Modem RXLine
Stat.
Int.
TX
Empty
Int
RX
Data
Int.
Stat.
Int.
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Enable Enable Enable Enable
0 1 0
ISR
RD
FIFOs
Enabled Enabled
FIFOs
0/
0/
INT
INT
INT
INT
LCR[7] = 0
Source Source Source Source
Bit-3
INT
INT
Bit-2
Bit-1
Bit-0
Source Source
Bit-5
Bit-4
0 1 0
FCR
WR RXFIFO RXFIFO
Trigger Trigger
0/
0/
DMA
Mode
TX
FIFO
RX
FIFOs
FIFO Enable
TXFIFO TXFIFO
Trigger Trigger
Enable Reset Reset
0 1 1
1 0 0
LCR RD/WR Divisor Set TX Set Par-
Even
Parity Enable
Parity
Stop
Bits
Word
Length Length
Bit-1 Bit-0
Word
Enable
Break
ity
MCR RD/WR
0/
0/
0/
Internal OP2#/ OP1# RTS# DTR#
Loop-
back
Enable Enable
IRQn
Output
Output Output
Control Control
BRG
Pres-
caler
IR Mode INTType
ENable Select
1 0 1
LSR
XFR
RD
RXFIFO
Error
TSR
Empty
THR
Empty
RX
Break
RX
RX
RX
Data
Over- Ready
run
RX
Data
Fram- Parity
ing
Error
Error
Error
LCR[7]=0
WR
Rsrvd
CD
Rsrvd
Enable
XonAny
LSR
INT
Auto
RS485 IR RX
Invert Enable
Invert
RS485
Control
Output
Half-
Mode Enable Input duplex
IR
1 1 0
1 1 1
MSR
RD
RI
DSR
CTS
Delta
CD#
Delta
RI#
Delta
DSR# CTS#
Delta
IRPW
WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
SPR RD/WR
24
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