ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
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REV. 5.0.0
2.18 Internal Loopback
The 650A UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 15 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto
RTS/CTS is not supported during internal loopback.
FIGURE 15. INTERNAL LOOP BACK
VCC
TX
Transmit Shift Register
(THR/FIFO)
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
RX
VCC
RTS#
RTS#
CTS#
CTS#
VCC
DTR#
DTR#
DSR#
DSR#
VCC
OP1#
OP1#
RI#
RI#
VCC
OP2#
OP2#
CD#
CD#
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