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ST16C650 参数 Datasheet PDF下载

ST16C650图片预览
型号: ST16C650
PDF下载: 下载PDF文件 查看货源
内容描述: 具有32字节FIFO 2.90V至5.5V UART [2.90V TO 5.5V UART WITH 32-BYTE FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 53 页 / 631 K
品牌: EXAR [ EXAR CORPORATION ]
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ST16C650A  
2.90V TO 5.5V UART WITH 32-BYTE FIFO  
áç  
REV. 5.0.0  
LCR[2]: TX and RX Stop-bit Length Select  
The length of the stop bit is specified by this bit in conjunction with the programmed word length.  
STOP BIT LENGTH  
(BIT TIME(S))  
WORD  
LENGTH  
BIT-2  
0
1
1
5,6,7,8  
5
1 (default)  
1-1/2  
2
6,7,8  
LCR[3]: TX and RX Parity Select  
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data  
integrity check. See Table 11 for parity selection summary below.  
Logic 0 = No parity.  
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the  
data character received.  
LCR[4]: TX and RX Parity Select  
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.  
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The  
receiver must be programmed to check the same format (default).  
Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1’s in the transmitted character.  
The receiver must be programmed to check the same format.  
LCR[5]: TX and RX Parity Select  
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.  
LCR BIT-5 = logic 0, parity is not forced (default).  
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive  
data.  
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive  
data.  
TABLE 11: PARITY SELECTION  
LCR BIT-5 LCR BIT-4 LCR BIT-3  
PARITY SELECTION  
No parity  
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Odd parity  
Even parity  
Force parity to mark, “1”  
Forced parity to space, “0”  
LCR[6]: Transmit Break Enable  
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a  
“space’, logic 0, state). This condition remains until disabled by setting LCR bit-6 to a logic 0.  
Logic 0 = No TX break condition (default).  
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line  
break condition.  
30  
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