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ST16C650 参数 Datasheet PDF下载

ST16C650图片预览
型号: ST16C650
PDF下载: 下载PDF文件 查看货源
内容描述: 具有32字节FIFO 2.90V至5.5V UART [2.90V TO 5.5V UART WITH 32-BYTE FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 53 页 / 631 K
品牌: EXAR [ EXAR CORPORATION ]
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ST16C650A  
2.90V TO 5.5V UART WITH 32-BYTE FIFO  
REV. 5.0.0  
2.9.1  
Transmit Holding Register (THR) - Write Only  
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host  
writes transmit data byte to the THR to be converted into a serial data stream including a start bit, data bits,  
parity bit and stop bit(s). The least-significant-bit (Bit-0) is the first data bit to go out. The THR is the input  
register to the transmit FIFO of 32 bytes when FIFO operation is enabled by FCR bit-0. Every time a write  
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data  
location.  
2.9.2  
Transmitter Operation in non-FIFO Mode  
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the  
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled  
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.  
FIGURE 9. TRANSMITTER OPERATION IN NON-FIFO MODE  
Transmit  
Holding  
Register  
(THR)  
Data  
Byte  
THR Interrupt (ISR bit-1)  
Enabled by IER bit-1  
16X Clock  
M
S
B
L
S
B
Transmit Shift Register (TSR)  
TXNOFIFO1  
2.9.3  
Transmitter Operation in FIFO Mode  
The host may fill the transmit FIFO with up to 32 bytes of transmit data. The THR empty flag (LSR bit-5) is set  
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the  
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by  
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.  
FIGURE 10. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE  
Transmit  
FIFO  
Transmit  
Data Byte  
THR Interrupt (ISR bit-1) falls  
below the programmed Trigger  
Level and then when becomes  
empty. FIFO is Enabled by FCR  
bit-0=1  
Auto CTS Flow Control (CTS# pin)  
Flow Control Characters  
(Xoff1/2 and Xon1/2 Reg.  
Auto Software Flow Control  
16X Clock  
Transmit Data Shift Register  
(TSR)  
TXFIFO1  
15  
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