ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Extended Mode Register Set-1 [EMRS(1)]
The EMRS(1) stores the data for enabling or disabling DLL, output driver strength, additive latency, ODT, disable DQS , OCD
program. The default value of the EMRS(1) is not defined, therefore EMRS(1) must be written after power up for proper operation.
The EMRS(1) is written by asserting LOW on CS , RAS , CAS , WE , BA1 and HIGH on BA0 (The device should be in all bank
Precharge with CKE already high prior to writing into EMRS(1)). The state of address pins A0~A12 in the same cycle as CS ,
RAS , CAS , WE and BA1 going LOW and BA0 going HIGH are written in the EMRS(1).
The tMRD time is required to complete the write operation to the EMRS(1). The EMRS(1) contents can be changed using the same
command and clock cycle requirements during normal operation as long as all banks are in the idle state. A0 is used for DLL
enable or disable. A1 is used for reducing output driver strength. The additive latency is defined by A3~A5. A7~A9 are used for
OCD control. A10 is used for DQS disable. ODT setting is defined by A2 and A6.
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
Rtt
A5
A4
A3
A2
A1
A0
0
1
Qoff
0*1
OCD program
Additive Latency
Rtt ODS DLL
DQS
A0
DLL Enable
0
1
Enable
Disable
A6 A2 Rtt (nominal)
0
0
0
1
Disable
75 Ω
A10
DQS Enable
150 Ω
50 Ω
1
1
0
1
Output Driver
Strength Control
Normal (100%)
Weak (60%)
A1
0
1
Enable
Disable
0
1
A12
Qoff*4
Additive Latency
0
1
Output buffer enable
Output buffer disable
A5 A4 A3
Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
Driver Impedance Adjustment
A9 A8 A7 OCD operation
BA1 BA0
Mode Register
0
0
1
1
0
1
0
1
MRS
EMRS(1)
EMRS(2)
EMRS(3): Reserved
OCD calibration
mode exit
Drive-1
Reversed
0
0
0
0
0
1
1
0
1
0
1
1
0
0
1
Drive-0
Adjustable mode*2
OCD default state*3
Note:
1. A11 is reserved for future use and must be set to 0.
2. When adjustable mode of driver impedance is issued, the previously set value of AL must be applied.
3. After setting to default state of driver impedance, OCD calibration mode needs to be exited by setting A9~A7 to 000.
4. Output disabled - DQs, DQSs, DQS s. This feature is used in conjunction with DIMM IDD measurements when IDDQ
is not desired to be included.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 28/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
