ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Mode Register Definition
Mode Register Set [MRS]
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst
length, burst type, test mode, DLL reset, WR and various vendor specific options to make the device useful for variety of different
applications. The default value of the mode register is not defined, therefore the mode register must be written after Power-Up for
proper operation. The mode register is written by asserting LOW on CS , RAS , CAS , WE , BA0 and BA1 (The device should
be in all bank Precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A12 in the
same cycle as CS , RAS , CAS , WE , BA0 and BA1 going LOW are written in the mode register.
The tMRD time is required to complete the write operation to the mode register. The mode register contents can be changed using
the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on functionality. The burst length is defined by A0 ~ A2. Burst address sequence
type is defined by A3, CAS latency (read latency from column address) is defined by A4 ~ A6. The DDR2 doesn’t support half clock
latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery
time WR is defined by A9 ~ A11. Refer to the table for specific codes.
BA1 BA0
A12
PD
A11 A10 A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
Mode Register
0
0
WR
DLL TM
Burst Length
CAS Latency
Active Power down exit timing
A7
Mode
A3 Burst Type
A12
PD
0
1
No
Yes
0
1
Sequential
Interleave
0
1
Fast Exit (normal)
Slow Exit (low power)
A8
DLL reset
BA1 BA0
Mode Register
A2 A1 A0
Burst Length
0
1
No
Yes
0
0
1
1
0
1
0
1
MRS
EMRS(1)
EMRS(2)
EMRS(3) : Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
CAS Latency
A6 A5 A4
Write recovery for Auto Precharge
Latency
A11 A10 A9
WR(cycles)*1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
3
4
5
6
7
8
3
4
5
6
7
Note:
1. WR(min.) (write recovery for Auto Precharge) is determined by tCK (max.) and WR(max.) is determined by tCK (min.)
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next
integer ( WR[cycles] = tWR (ns)/ tCK (ns)). The mode register must be programmed to this value. This is also used with
t
RP to determine tDAL.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 26/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
