ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Command Truth Table
Note 7
Note 7
A12~A11,
COMMAND
DM BA0,1 A10/AP
Note
1,2
CS RAS CAS
WE
L
CKE(n-1) CKE(n)
A9~A0
(Extended) Mode Register Set
Auto Refresh
H
H
H
H
L
L
L
L
L
L
L
X
X
OP CODE
X
H
Entry
10,12
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
6,9,
12
Exit
L
H
H
X
X
X
Bank Active
Read
H
V
V
Row Address
Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
H
H
H
H
L
H
L
H
X
X
1,3
1,3
(A9~A0)
Column
Address
Write
L
L
H
L
L
L
L
V
H
(A9~A0)
Bank Selection
All Banks
V
X
L
Precharge
H
H
L
H
L
H
X
X
X
X
X
X
H
H
L
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
4,11,
12,15
Entry
Active Power-Down
X
X
H
L
4,8,
12,15
Exit
H
L
H
L
4,11,
12,15
Entry
Exit
H
L
Precharge Power-Down
H
L
4,8,
12,15
H
DM
H
H
H
H
X
X
X
V
X
X
X
X
X
16
Device Deselect
No Operation
H
L
X
H
X
H
X
H
(OP code = Operand Code, V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note:
1. BA during a MRS/EMRS command selects which mode register is programmed.
2. MRS/EMRS can be issued only at all bank Precharge state.
3. Burst Reads or Writes at BL = 4 cannot be terminated or interrupted.
4. The Power-Down mode does not perform any Refresh operations. The duration of Power-Down is limited by the Refresh
requirements. Need one clock delay to entry and exit mode.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. Self Refresh Exit is asynchronous.
7. CKE (n) is the logic state of CKE at clock edge n; CKE (n–1) was the state of CKE at the previous clock edge.
8. All states not shown are illegal or reserved unless explicitly described elsewhere in this document.
9. On Self Refresh, Exit Deselect or NOP commands must be issued on every clock edge occurring during the tXSNR period.
Read commands may be issued only after tXSRD is satisfied.
10. Self Refresh mode can only be entered from all banks Idle state.
11. Power-Down and Self Refresh can not be entered while Read or Write operations, MRS/EMRS operations or Precharge
operations are in progress.
12. Minimum CKE HIGH / LOW time is tCKE (min).
13. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
14. CKE must be maintained HIGH while the device is in OCD calibration mode.
15. ODT must be driven HIGH or LOW in Power-Down if the ODT function is enabled.
16. Used to mask write data, provided coincident with the corresponding data.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 24/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
