ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Burst Address Ordering for Burst Length
Burst
Starting Column Address
Sequential Mode
Interleave Mode
Length
(A2, A1,A0)
000
0, 1, 2, 3
0, 1, 2, 3
001
1, 2, 3, 0
1, 0, 3, 2
4
010
2, 3, 0, 1
2, 3, 0, 1
011
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
001
010
011
8
100
101
110
111
Mode Register Set
0
1
2
3
4
5
6
7
8
C L K
C L K
* 1
A n y
C o m m a n d
M o d e
R e g i s t e r S e t
P r e c h a r g e
A l l B a n k s
C O MM A N D
* 2
R P
t
C K
t
t
M R D
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal
operation after having the DLL disabled for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is
enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_18. The device also supports a weak drive strength option,
intended for lighter load and/or point-to-point environments.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 27/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
