ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Power On and Initialization
DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified
may result in undefined operation.
Power-Up and Initialization Sequence
The following sequence is required for Power-Up and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 x VDDQ and ODT (*1) at a low state (all other inputs may be undefined).
-
-
VDD(*2), VDDL(*2) and VDDQ are driven from a single power converter output, AND
VTT is limited to 0.95V max, AND
-
VREF tracks VDDQ /2.
or
-
Apply VDD(*2) before or at the same time as VDDL
.
-
Apply VDDL(*2) before or at the same time as VDDQ
.
-
Apply VDDQ before or at the same time as VTT and VREF
.
at least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200us after stable power and clock (CLK, CLK ), then apply NOP or Deselect and take CKE High.
4. Waiting minimum of 400ns then issue Precharge commands for all banks of the device. NOP or Deselect applied during
400ns period.
5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “LOW” to BA0, “HIGH” to BA1.)
6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “HIGH” to BA0 and BA1.)
7. Issue EMRS(1) to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and "LOW" to
BA1.)
8. Issue a Mode Register Set command for “DLL reset” (*3).
(To issue DLL reset command, provide “HIGH” to A8 and “LOW” to BA0-1)
9. Issue Precharge commands for all banks of the device.
10. Issue 2 or more Auto Refresh commands.
11. Issue a Mode Register Set command with LOW to A8 to initialize device operation. (To program operation parameters without
resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD calibration (Off Chip Driver impedance adjustment).
If OCD calibration is not used, EMRS(1) OCD default command (A9=A8= A7=1) followed by EMRS(1) OCD calibration
mode exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS(1).
13. The DDR2 SDRAM is now ready for normal operation.
Note :
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
*2) If DC voltage level of VDDL or VDD is intentionally changed during normal operation, (for example, for the purpose of VDD
corner test, or power saving) “DLL Reset” must be executed.
*3) Every “DLL enable” command resets DLL. Therefore sequence 8 can be skipped during power up. Instead of it, the
additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Initialization Sequence after Power-UP
t
C H
tC L
C L K
C L K
t
I S
C K E
A n
y
E M RS ( 1 )
E M R S ( 2)
E M R S ( 3 )
E M RS (1 )
C o m m a n d
PALL
E M R S ( 1 )
NOP
MRS
PALL
REF
REF
MRS
C o m m a n d
t
R P
t
M R D
t
M R D
t
M R D
t
M R D
t
R P
t
R F C
t
R F C
t
M R D
F o l l o w O C D
F l o w C h a r t
tO I T
4 0 0 n s
P r e c h a r g e
A l l
O C D C a l i b r a t i o n
m o d e e x i t
D L L e n a b l e
O C D d e f a u l t
D L L R e s e t
2 0 0 C y c l e ( m i n . )
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 25/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
