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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
OCD Adjustable Mode  
CLK  
CLK  
EMRS(1)  
EMRS(1)  
Command  
DQS, DQS  
DQ  
NOP  
DT2  
NOP  
t
WR  
WL  
t
DS  
t
DH  
DT0  
DT1  
DT3  
DM  
OCD adjustable  
OCD calibration mode exit  
Note: For proper operation of adjustable mode, WL = RL - 1 = AL + CL - 1 clocks and tDS / tDH should be met as the  
above timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by  
MRS addressing mode (ie. sequential or interleave).  
OCD Driver Mode  
CLK  
CLK  
EMRS(1)  
EMRS(1)  
Command  
DQS, DQS  
DQ  
NOP  
High-Z  
High-Z  
DQs high and DQS low for Drive-1, DQs low and DQS high for Drive-0  
DQs high for Drive-1  
DQs low for Drive-0  
tOIT  
t
OIT  
Enter drive mode  
OCD Calibration mode exit  
Note: Drive mode, both Drive-1 and Drive-0, is used for controllers to measure DDR2 SDRAM driver impedance. In  
this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are  
turned-off tOIT after “OCD calibration mode exit” command as the above timing diagram.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1 32/62  
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