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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
EMRS(1) for OCD Impedance Adjustment  
OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode, all outputs are driven out by DDR2  
SDRAM. In Drive-1mode, all DQ, DQS signals are driven HIGH and all DQS signals are driven LOW. In Drive-0 mode, all DQ,  
DQS signals are driven LOW and all DQS signals are driven HIGH. In adjustable mode, BL = 4 of operation code data must be  
used. In case of OCD default state, output driver characteristics have a nominal impedance value of 18 during nominal  
temperature and voltage conditions. Output driver characteristics for OCD default state are specified in OCD default characteristics  
table. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if weak strength is set or adjustable  
mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is  
set to default, subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in order to  
maintain the default or calibrated value.  
Driver Impedance Adjustment Mode  
A9  
0
A8  
0
A7  
0
Operation  
OCD calibration mode exit  
0
0
1
Device-1: DQ,DQS High and DQS Low  
0
1
0
Device-0: DQ,DQS Low and DQS High  
Adjustable mode  
OCD default state  
1
1
0
1
0
1
Adjust OCD Impedance  
To adjust output driver impedance, controllers must issue EMRS(1) command for adjustable mode along with a 4bit burst code to  
DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before  
activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in the following table means all DQ bits  
at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DQs simultaneously and after OCD  
calibration, all DQs of a given device will be adjusted to the same driver strength setting.  
The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect.  
The default setting may be any step within the 16 step range. When Adjustable mode command is issued, AL from previously set  
value must be applied.  
OCD Adjustment Table  
DT0  
0
DT1  
0
DT2  
0
DT3  
0
Pull-up driver strength  
NOP  
Pull-down driver strength  
NOP  
0
0
0
0
0
1
0
1
0
1
0
0
Increase by 1 step  
Decrease by 1 step  
NOP  
NOP  
NOP  
Increase by 1 step  
Decrease by 1 step  
Increase by 1 step  
Increase by 1 step  
Decrease by 1 step  
Decrease by 1 step  
Reserve  
1
0
0
1
0
1
1
0
0
0
1
0
0
1
0
1
NOP  
Increase by 1 step  
Decrease by 1 step  
Increase by 1 step  
Decrease by 1 step  
Reserve  
1
0
1
0
Others  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1 31/62  
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