Epson Research and Development
Page 79
Vancouver Design Center
7.4.2 Power Save Mode
Power Save
Mode Enable Bit
(REG[1F0h] bit 0)
FPFRAME
t1
t2
t4
t3
t5
FPLINE, FPSHIFT
FPDATA, DRDY
t6
t8
LCD Power Save
Status Bit
(REG[1F1h] bit 1)
t7
t9
Memory Controller
Power Save Status Bit
(REG[1F1h] bit 0)
allowed
allowed
not allowed
Memory Access
Figure 7-21: Power Save Mode Timing
Note
Memory accesses cannot be performed after a Power Save Mode has been initiated.
Note
The Memory Controller Power Save Status Bit will go high only if the Refresh Select
Bits (REG[021h] bits 7-6) are set to Self-Refresh or No Refresh.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
