Epson Research and Development
Page 167
Vancouver Design Center
BitBlt Width Register 1
REG[111h]
RW
BitBlt Width
Bit 9
BitBlt Width
Bit 8
n/a
n/a
n/a
n/a
n/a
n/a
REG[110h] bits 7-0
REG[111h] bits 1-0
BitBlt Width Bits [9:0]
A 10-bit register that specifies the BitBlt width in pixels -1.
Note
The BitBlt operations Pattern Fill with ROP and Pattern Fill with transparency require a
BitBlt width ≥ 2.
BitBlt Height Register 0
REG[112h]
RW
BitBlt Height
Bit 7
BitBlt Height
Bit 6
BitBlt Height
Bit 5
BitBlt Height
Bit 4
BitBlt Height
Bit 3
BitBlt Height
Bit 2
BitBlt Height
Bit 1
BitBlt Height
Bit 0
BitBlt Height Register 1
REG[113h]
RW
BitBlt Height
Bit 9
BitBlt Height
Bit 8
n/a
n/a
n/a
n/a
n/a
n/a
REG[112h] bits 7-0
REG[113h] bits 1-0
BitBlt Height Bits [9:0]
A 10-bit register that specifies the BitBlt height in lines -1.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
