Page 164
Epson Research and Development
Vancouver Design Center
BitBlt Operation Register
REG[103h]
RW
BitBlt
Operation
Bit 3
BitBlt
Operation
Bit 2
BitBlt
Operation
Bit 1
BitBlt
Operation
Bit 0
n/a
n/a
n/a
n/a
bits 3-0
BitBlt Operation Bits [3:0]
Specifies the 2D Operation to be carried out based on the following table:
Table 8-32: BitBlt Operation Selection
BitBlt Operation Bits [3:0]
Blit Operation
Write Blit with ROP.
0000
0001
Read Blit.
0010
Move Blit in positive direction with ROP.
Move Blit in negative direction with ROP.
Transparent Write Blit.
0011
0100
0101
Transparent Move Blit in positive direction.
Pattern Fill with ROP.
0110
0111
Pattern Fill with transparency.
Color Expansion.
1000
1001
Color Expansion with transparency.
Move Blit with Color Expansion.
Move Blit with Color Expansion and transparency.
Solid Fill.
1010
1011
1100
Other combinations
Reserved
Note
The BitBlt operations Pattern Fill with ROP and Pattern Fill with transparency require a
BitBlt width ≥ 2. The BitBlt width is set in REG[110h], REG[111h].
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
