Page 166
Epson Research and Development
Vancouver Design Center
BitBlt Destination Start Address Register 0
REG[108h]
RW
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BitBlt Destination Start Address Register 1
REG[109h]
RW
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
BitBlt Destination Start Address Register 2
REG[10Ah]
RW
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
Destination
Destination
Destination
Destination
Destination
n/a
n/a
n/a
Start Address Start Address Start Address Start Address Start Address
Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
REG[108h] bits 7-0
REG[109h] bits 7-0
BitBlt Destination Start Address Bits [20:0]
A 21-bit register that specifies the destination start address for the BitBlt operation.
REG[10Ah] bits 4-0
BitBlt Memory Address Offset Register 0
REG[10Ch]
RW
BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory
Address
Address
Address
Address
Address
Address
Address
Address
Offset Bit 7
Offset Bit 6
Offset Bit 5
Offset Bit 4
Offset Bit 3
Offset Bit 2
Offset Bit 1
Offset Bit 0
BitBlt Memory Address Offset Register 1
REG[10Dh]
RW
BitBlt Memory BitBlt Memory BitBltMemory
n/a
n/a
n/a
n/a
n/a
Address
Address
Address
Offset Bit 10
Offset Bit 9
Offset Bit 8
REG[10Ch] bits 7-0
REG[10Dh] bits 2-0
BitBlt Memory Address Offset Bits [10:0]
These bits are the display’s 11-bit address offset from the starting word of line “n” to the
starting word of line “n + 1”. They are used only for address calculation when the Blit is
configured as a rectangular region of memory. They are not used for the displays.
BitBlt Width Register 0
REG[110h]
RW
BitBlt Width
Bit 7
BitBlt Width
Bit 6
BitBlt Width
Bit 5
BitBlt Width
Bit 4
BitBlt Width
Bit 3
BitBlt Width
Bit 2
BitBlt Width
Bit 1
BitBlt Width
Bit 0
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
