Page 162
Epson Research and Development
Vancouver Design Center
bit 6
BitBlt FIFO Not-Empty Status
This is a read-only status bit.
When this bit = 1, the BitBlt FiFO has at least one data.
When this bit = 0, the BitBlt FIFO is empty.
To reduce system memory read latency, software can monitor this bit prior to a BitBlt read
burst operation.
The following table shows the number of data available in BitBlt FIFO under different
status conditions.
Table 8-30: BitBlt FIFO Data Available
BitBlt FIFO Full
Status (REG[100h]
Bit 4)
BitBlt FIFO Half
Full Status
(REG[100h] Bit 5) (REG[100h] Bit 6)
BitBlt FIFO Not
Empty Status
Number of Data
available in BitBlt
FIFO
0
0
0
1
0
0
1
1
0
1
1
1
0
1 to 6
7 to 14
15 to 16
bit 5
bit 4
bit 1
bit 0
BitBlt FIFO Half Full Status
This is a read-only status bit.
Software can use this bit to optimize BitBlt write burst operations.
When this bit = 1, the BitBlt FIFO is half full or greater than half full.
When this bit = 0, the BitBlt FIFO is less than half full.
BitBlt FIFO Full Status
This is a read-only status bit.
Software can use this bit to optimize BitBlt write burst operations.
When this bit = 1, the BitBlt FIFO is full.
When this bit = 0, the BitBlt FIFO is not full.
BitBlt Destination Linear Select
When this bit = 1, the Destination Blit is stored as a contiguous linear block of memory.
When this bit = 0, the Destination Blit is stored as a rectangular region of memory.
The BitBlt Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address
offset from the start of one line to the next line.
BitBlt Source Linear Select
When this bit = 1, the Source Blit is stored as a contiguous linear block of memory.
When this bit = 0, the Source Blit is stored as a rectangular region of memory.
The BitBlt Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address
offset from the start of one line to the next line.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
