Page 136
Epson Research and Development
Vancouver Design Center
MOD Rate Register
REG[031h]
RW
MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit
n/a
n/a
5
4
3
2
1
0
bits 5-0
MOD Rate Bits [5:0]
For a non-zero value these bits specify the number of FPLINE between toggles of the
MOD output signal (DRDY).
When these bits are all 0’s the MOD output signal toggles every FPFRAME. These bits
are for passive LCD panels only.
LCD Horizontal Display Width Register
REG[032h]
RW
LCD
Horizontal
LCD
Horizontal
LCD
Horizontal
LCD
Horizontal
LCD
Horizontal
LCD
Horizontal
LCD
Horizontal
n/a
Display Width Display Width Display Width Display Width Display Width Display Width Display Width
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
bits 6-0
LCD Horizontal Display Width Bits [6:0]
These bits specify the LCD panel horizontal display width, in 8 pixel resolution.
Horizontal display width in number of pixels = ((ContentsOfThisRegister)+ 1) × 8
The Horizontal Display Width has certain limitations on the values that may be used for
each type of LCD panel. Use of values that do not meet the limitations listed in the
following table will result in undefined behavior.
Table 8-16: Horizontal Display Width (Pixels)
Panel Type
Passive Single
Passive Dual
TFT
Horizontal Display Width (Pixels)
must be divisible by 16
must be divisible by 32
must be divisible by 8
Note
This register must be programmed such that REG[032h] ≥ 3 (32 pixels).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
