Page 138
Epson Research and Development
Vancouver Design Center
TFT FPLINE Pulse Width Register
REG[036h]
RW
LCD FPLINE
TFT FPLINE TFT FPLINE TFT FPLINE TFT FPLINE
Polarity
Select
n/a
n/a
n/a
Pulse Width
Bit 3
Pulse Width
Bit 2
Pulse Width
Bit 1
Pulse Width
Bit 0
bit 7
LCD FPLINE Polarity Select
This bit selects the polarity of FPLINE for all LCD panels.
When this bit = 1, the FPLINE pulse is active high for TFT/D-TFD and active low for pas-
sive LCD.
When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and active high for pas-
sive LCD.
Table 8-17: LCD FPLINE Polarity Selection
LCD FPLINE Polarity Select Passive LCD FPLINE Polarity
TFT FPLINE Polarity
active low
0
1
active high
active low
active high
bits 3-0
TFT FPLINE Pulse Width Bits [3:0]
For TFT/D-TFD panel only, these bits specify the pulse width of the FPLINE output sig-
nal in 8 pixel resolution.
FPLINE pulse width in number of pixels = ((ContentsOfThisRegister) + 1) × 8
The maximum FPLINE pulse width is 128 pixels.
Note
For TFT/D-TFD only:
REG[034h] + 1 ≥ (REG[035h] + 1) + (REG[036h] bits 3-0 + 1)
LCD Vertical Display Height Register 0
REG[038h]
RW
LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical LCD Vertical
Display
Display
Display
Display
Display
Display
Display
Display
Height Bit 7
Height Bit 6
Height Bit 5
Height Bit 4
Height Bit 3
Height Bit 2
Height Bit 1
Height Bit 0
LCD Vertical Display Height Register 1
REG[039h]
RW
LCD Vertical LCD Vertical
n/a
n/a
n/a
n/a
n/a
n/a
Display
Display
Height Bit 9
Height Bit 8
REG[038h] bits 7-0
REG[039h] bits 1-0
LCD Vertical Display Height Bits [9:0]
These bits specify the LCD panel vertical display height, in 1 line resolution.
Vertical display height in number of lines = (ContentsOfThisRegister) + 1
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
