Epson Research and Development
Page 137
Vancouver Design Center
LCD Horizontal Non-Display Period Register
REG[034h]
RW
LCD
LCD
LCD
LCD
LCD
Horizontal
Non-Display
Period Bit 4
Horizontal
Non-Display
Period Bit 3
Horizontal
Non-Display
Period Bit 2
Horizontal
Non-Display
Period Bit 1
Horizontal
Non-Display
Period Bit 0
n/a
n/a
n/a
bits 4-0
LCD Horizontal Non-Display Period Bits [4:0]
These bits specify the LCD panel horizontal non-display period width in 8 pixel resolu-
tion.
Horiz. non-display period width in number of pixels = ((ContentsOfThisRegister) + 1) × 8
Note
This register must be programmed such that REG[032h] ≥ 3 (32 pixels).
Note
For TFT/D-TFD only:
REG[034h] + 1 ≥ (REG[035h] + 1) + (REG[036h] bits 3-0 + 1)
TFT FPLINE Start Position Register
REG[035h]
RW
TFT FPLINE TFT FPLINE TFT FPLINE TFT FPLINE TFT FPLINE
Start Position Start Position Start Position Start Position Start Position
n/a
n/a
n/a
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
bits 4-0
TFT FPLINE Start Position Bits [4:0]
For TFT/D-TFD panel only, these bits specify the delay, in 8 pixel resolution, from the
start of the horizontal non-display period to the leading edge of the FPLINE pulse.
For 4/8 bpp color depth:
FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 4]
For 15/16 bpp color depth:
FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 6]
Note
For TFT/D-TFD only:
REG[034h] + 1 ≥ (REG[035h] + 1) + (REG[036h] bits 3-0 + 1)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
